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12-bit, integrated, multiformat sdtv/hdtv video decoder and rgb gr aphics digitizer adv7403 rev. spa information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features four noise shaped video ? 12-bit adcs sampling up to 140 mhz (140 mhz speed grade only) 12 analog input channel mux scart fast blank support internal antialias filters ntsc/pal/secam color standards support 525p-/625p-component prog ressive scan support 720p-/1080i-component hdtv support digitizes rgb graphics up to 1280 1024 @ 75 hz (sxga) (140 mhz speed grade only) 24-bit digital input port supports data from dvi/hdmi rx ic any-to-any, 3 3 color- space conversion matrix industrial temperature range (?40c to +85c) 12-bit 4:4:4/10-/8-bit 4:2:2 ddr pixel output interface programmable interrupt request output pin vbi data slicer (including teletext) applications lcd/dlp? rear projection hdtvs pdp hdtvs crt hdtvs lcd/dlp front projectors lcd tv (hdtv ready) hdtv stbs with pvr hard-disk-based video recorders multiformat scan converters dvd recorders with progressive scan input support avr receiver general description the adv7403 is a high quality, single chip, multiformat video decoder and graphics digitizer. this multiformat decoder supports the conversion of pal, ntsc, and secam standards in the form of composite or s-video into a digital itu-r bt.656 format. the adv7403 also supports the decoding of a component rgb/yprpb video signal into a digital ycrcb or rgb pixel output stream. the support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, and many other hd and smpte standards. graphic digitization is also supported by the adv7403; it is capable of digitizing rgb graphics signals from vga to sxga rates and converting them into a digital rgb or ycrcb pixel output stream. scart and overlay functionality are enabled by the adv7403s ability to simultaneously process cvbs and standard definition rgb signals. the mixing of these signals is controlled by the fast blank pin. the adv7403 contains two main processing sections. the first is the standard definition processor (sdp), which processes all pal, ntsc, and secam signal types. the second is the component processor (cp), which processes yprpb and rgb component formats, including rgb graphics. for more specific descriptions of the adv7403 features, see the detailed functionality and detailed description sections.
adv7403 rev. spa | page 2 of 24 table of contents functional block diagram .............................................................. 3 electrical characteristics ................................................................. 4 video specifications ......................................................................... 6 timing characteristics ..................................................................... 7 analog specifications ....................................................................... 8 absolute maximum ratings ............................................................ 9 stress ratings ................................................................................ 9 package thermal performance ................................................... 9 thermal specifications ................................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 timing diagrams ............................................................................ 12 detailed functionality ................................................................... 13 analog front end ....................................................................... 13 sdp pixel data output modes ................................................. 13 cp pixel data output modes ................................................... 13 composite and s-video processing ......................................... 13 component video processing .................................................. 14 rgb graphics processing ......................................................... 14 digital video input port ............................................................ 14 general features ......................................................................... 14 detailed description ...................................................................... 15 analog front end ....................................................................... 15 standard definition processor ................................................. 15 component processor ............................................................... 15 pixel input/output formatting .................................................... 17 recommended external loop filter components .................... 19 typical connection diagram ....................................................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 9/05rev. sp0 to rev. spa deleted edtv.....................................................................universal added avr receiver to applications section.............................. 1 change to crystal normal frequency typ value in table 3 ...... 7 changes to figure 2 ....................................................................... 10 changes to function descriptions of pin 37 and pin 38 .......... 11 change pin 70 type........................................................................ 11 change to crystal mhz unit value ............................................. 13 added pixel input information to table 9 and table 10 ........... 17 changes to figure 9........................................................................ 20 4/05revision sp0: initial version
adv7403 rev. spa | page 3 of 24 functional block diagram input mux data preprocessor decimation and downsampling filters standard defi nition processor luma filter output fifo and formatter ain1 to ain12 adv7403 serial interface control and vbi data sclk sda alsb sync extract 20 hs 8 8 p29?p20 p19?p10 p9?p0 pixel data vs field/de llc1 sfl/ syncout cvbs s-video yprpb scart? (rgb + cvbs) graphics rgb 12 chroma filter chroma demod f sc recovery int luma resample luma 2d comb (5h max) resample control chroma resample chroma 2d comb (4h max) fast blank overlay control and av code insertion fb y cb cr vbi data recovery macrovision detection standard autodetection cvbs/y c cb cr cb y colorspace conversion cvbs cr 8 component processor sclk2 sda2 sspd stdi sync processing and clock generation dclk_in de_in hs_in vs_in sog soy digital input port dvi or hdmi xtal xtal1 24 8 8 8 digital fine clamp gain control offset control av code insertion 30 12 12 12 12 12 12 12 active peak and agc macrovision detection cgms data extraction p40?p31 p29?p20 p11?p10 p1?p0 12 a/d clamp anti- alias filter 12 a/d clamp anti- alias filter 12 a/d clamp anti- alias filter 12 a/d clamp anti- alias filter 05431-001 figure 1.
adv7403 rev. spa | page 4 of 24 electrical characteristics @ avdd = 3.15 v to 3.45 v, dvdd = 1.65 v to 2.0 v, dvddio = 3.0 v to 3.6 v, pvdd = 1.71 v to 1.89 v, nominal input range 1.6 v. operating temperature range, a otherwise noted. table 1. parameter 1 , , 2 3 symbol test conditions min typ max unit static performance 4 , 5 resolution (each adc) n 12 bits integral nonlinearity inl bsl at 27 mhz (at a 12-bit level) 2.0 8.0 lsb integral nonlinearity inl bsl at 54 mh z (at a 12-bit level) ?2.0/+2.5 lsb integral nonlinearity inl bsl at 74 mhz (at a 10-bit level) 1.0 lsb integral nonlinearity inl bsl at 110 mh z (at a 10-bit level) ?3.0/+3.0 lsb integral nonlinearity inl bsl at 135 mhz (at an 8-bit level) 6 1.3 lsb differential nonlinearity dnl at 27 mhz (at a 12-bit level) ?0.7/+0.85 ?0.99/+2.5 lsb differential nonlinearity dnl at 54 mhz (at a 12-bit level) ?0.75/+0.9 lsb differential nonlinearity dnl at 74 mhz (at a 10-bit level) 0.75 lsb differential nonlinearity dnl at 110 mhz (at a 10-bit level) ?0.7/+5.0 lsb differential nonlinearity dnl at 135 mhz (at an 8-bit level) 6 ?0.8/+2.5 lsb digital inputs input high voltage 7 v ih 2 v input low voltage 8 v il 0.8 v input high voltage v ih hs_in, vs_in low trigger mode 0.7 v input low voltage v il hs_in, vs_in low trigger mode 0.3 v input current i in pins listed in note 9 ?60 +60 a all other input pins ?10 +10 a input capacitance 10 c in 10 pf digital outputs output high voltage 11 v oh isource = 0.4 ma 2.4 v output low voltage 11 v ol isink = 3.2 ma 0.4 v high impedance leakage current i leak pins listed in note 12 60 a all other output pins 10 a output capacitance 10 c out 20 pf power requirements 10 digital core power supply dvdd 1.65 1.8 2 v digital i/o power supply dvddio 3.0 3.3 3.6 v pll power supply pvdd 1.71 1.8 1.89 v analog power supply avdd 3.15 3.3 3.45 v digital core supply current idvdd cvbs input sampling at 54 mhz 105 ma graphics rgb sampling at 135 mhz 137 ma scart rgb fb sampling at 54 mhz 106 ma digital i/o supply current idvddio cvbs input sampling at 54 mhz 4 ma graphics rgb sampling at 135 mhz 19 ma pll supply current ipvdd cvbs input sampling at 54 mhz 11 ma graphics rgb sampling at135 mhz 12 ma analog supply current 13 iavdd cvbs input sampling at 54 mhz 99 ma graphics rgb sampling at 135 mhz 242 ma scart rgb fb sampling at 54 mhz 269 ma power-down current ipwrdn 2.25 ma green mode power-down ipwrdng sync bypass function 16 ma power-up time tpwrup 20 ms 1 the min/max specifications are guaranteed over this range. 2 temperature range t min to t max : ?40c to +85c (0c to 70c temperature ra nge for adv7403kstz-140). 3 all specifications obtained using programming scripts with the fo llowing sequence included: addr 0x0e - data 0x80, addr 0x54 - data 0x00, addr 0x0e - data 0x00.
adv7403 rev. spa | page 5 of 24 4 all adc linearity tests performed at input range of full scale ? 12.5%, and at zero scale + 12.5%. 5 max inl and dnl specifications obtained wi th part configured for co mponent video input. 6 specification for adv7403kstz-140 only. 7 to obtain specified v ih level on pin 38, register 0x13 (wo) mu st be programmed with value 0x04. if regi ster 0x13 is programmed with value 0x00, then v ih on pin 38 = 1.2 v. 8 to obtain specified v il level on pin 38, register 0x13 (wo) mu st be programmed with value 0x04. if regi ster 0x13 is programmed with value 0x00, then v il on pin 38 = 0.4 v. 9 pins 1, 2, 13, 14, 16, 19, 24, 29, 30, 31, 32, 33, 34, 35, 45, 78, 79, 83, 84, 87, 88, 95, 96, 97, 100. 10 guaranteed by characterization. 11 v oh and v ol levels obtained using default drive strength value (0xd5) in register subaddress 0xf4. 12 pins 3, 13, 14, 19, 24, 29, 30, 31, 32, 33, 34, 45. 13 analog current measurements for cvbs made with adc0 powered up only, for rgb, adc0, adc1, and adc2 powered up only, for scart fb, all adcs powered up.
adv7403 rev. spa | page 6 of 24 video specifications @ avdd= 3.15 v to 3.45 v, dvdd = 1.65 v to 2.0 v, dvddio = 3.0 v to 3.6 v, pvdd = 1.71 v to 1.89 v. operating temperature range , unless otherwise noted. table 2. parameter 1 , , 2 3 symbol test conditions min typ max unit nonlinear specifications differential phase dp cvbs input, modulated 5 step 0.4 degree differential gain dg cvbs input, modulated 5 step 0.4 % luma nonlinearity lnl cvbs input, 5 step 0.4 % noise specifications snr unweighted luma ramp 61 64 db snr unweighted luma flat field 64 65 db analog front end crosstalk 60 db lock time specifications horizontal lock range ?5 +5 % vertical lock range 40 70 hz f sc subcarrier lock range 1.3 khz color lock in time 60 line sync depth range 4 20 200 % color burst range 5 200 % vertical lock time 2 field horizontal lock time 100 line chroma specifications hue accuracy hue 1 degree color saturation accuracy cl_ac 1 % color agc range 5 400 % chroma amplitude error 0.4 % chroma phase error 0.3 degree chroma luma intermodulation 0.1 % luma specifications luma brightness accuracy cvbs, 1 v input 1 % luma contrast accuracy cvbs, 1 v input 1 % 1 the min/max specifications are guaranteed over this range. 2 temperature range t min to t max : ?40c to +85c (0c to 70c temperature ra nge for adv7403kstz-140). 3 guaranteed by characterization. 4 nominal sync depth is 300 mv at 100% sync depth range.
adv7403 rev. spa | page 7 of 24 timing characteristics @ avdd = 3.15 v to 3.45 v, dvdd = 1.65 v to 2.0 v, dvddio = 3.0 v to 3.6 v, pvdd = 1.71 v to 1.89 v. operating temperature rang e, unless otherwise noted. table 3. parameter 1 , , 2 3 symbol test conditions min typ max unit system clock and crystal crystal nominal frequency 28.63636 mhz crystal frequency stability 50 ppm horizontal sync input frequency 14.8 110 khz llc1 frequency range 4 12.825 140 mhz i 2 c port 5 sclk frequency 400 khz sclk min pulse width high t 1 0.6 s sclk min pulse width low t 2 1.3 s hold time (start condition) t 3 0.6 s setup time (start condition) t 4 0.6 s sda setup time t 5 100 ns sclk and sda rise time t 6 300 ns sclk and sda fall time t 7 300 ns setup time for stop condition t 8 0.6 s reset feature reset pulse width 5 ms clock outputs llc1 mark space ratio t 9 :t 10 45:55 55:45 % duty cycle data and control outputs data output transition time sdr (sdp) 6 t 11 negative clock edge to start of valid data 3.6 ns data output transition time sdr (sdp) 6 t 12 end of valid data to negative clock edge 2.4 ns data output transition time sdr (cp) 7 t 13 end of valid data to negative clock edge 2.8 ns data output transition time sdr (cp) 7 t 14 negative clock edge to start of valid data 0.1 ns data output transition time ddr (cp) 7 , 8 t 15 positive clock edge to end of valid data ?4 + tllc1/4 ns data output transition time ddr (cp) 7 , 8 t 16 positive clock edge to start of valid data 0.25 + tllc1/4 ns data output transition time ddr (cp) 7 , 8 t 17 negative clock edge to end of valid data ?2.95 + tllc1/4 ns data output transition time ddr (cp) 7 , 8 t 18 negative clock edge to start of valid data ?0.5 + tllc1/4 ns data and control inputs 5 input setup time (dig ital input port) t 19 hs_in, vs_in 9 ns de_in, data inputs 2.2 ns input hold time (digital input port) t 20 hs_in, vs_in 7 ns de_in, data inputs 2 ns 1 the min/max specifications are guaranteed over this range. 2 temperature range t min to t max : ?40c to +85c (0c to 70c temperature ra nge for adv7403kstz-140). 3 guaranteed by characterization. 4 maximum llc1 frequency is 110 mhz for adv7403bstz-110. 5 ttl input values are 0 v to 3 v, with rise/fall times 3 ns, measured between the 10% and 90% points. 6 sdp timing figures obtained using default drive strength value (0xd5) in register subaddress 0xf4. 7 cp timing figures obtain ed using max drive strength value (0 xff) in register subaddress 0xf4. 8 ddr timing specifications dependent on llc1 output pixel clock; tlcc1/4 = 9.25 ns at llc1 = 27 mhz.
adv7403 rev. spa | page 8 of 24 analog specifications @ avdd = 3.1.5 v to 3.45 v, dvdd = 1.65 v to 2.0 v, dvddio = 3.0 v to 3.6 v, pvdd = 1.71 v to 1.89 v. operating temperature range, unless otherwise noted. recommended analog input video signal range: 0.5 v to 1.6v , typically 1 v p-p. table 4. parameter 1 , , 2 3 test conditions min typ max unit clamp circuitry external clamp capacitor 0.1 f input impedance 4 clamps switched off 10 m input impedance of pin 51 (fb) 20 k cml 1.86 v adc full-scale level cml + 0.8 v v adc zero-scale level cml ? 0.8 v v adc dynamic range 1.6 v clamp level (when locked) cvbs input cml ? 0.292 v v scart rgb input (r, g, b signals) cml ? 0.4 v v s-video input (y signal) cml ? 0.292 v v s-video input (c signal) cml C 0 v v component input (y, pr, pb signals) cml C 0.3 v v pc rgb input (r, g, b signals) cml ? 0.3 v v large clamp source current sdp only 0.75 ma large clamp sink current sdp only 0.9 ma fine clamp source current sdp only 17 a fine clamp sink current sdp only 17 a 1 the min/max specifications are guaranteed over this range. 2 temperature range t min to t max :?40c to +85c (0c to 70c temperature range for adv7403kstz-140). 3 guaranteed by characterization. 4 except pin 51 (fb).
adv7403 rev. spa | page 9 of 24 absolute maximum ratings stress ratings table 5. parameter rating avdd to agnd 4 v dvdd to dgnd 2.2 v pvdd to agnd 2.2 v dvddio to dgnd 4 v dvddio to avdd ?0.3 v to +0.3 v pvdd to dvdd ?0.3 v to +0.3 v dvddio to pvdd ?0.3 v to +2 v dvddio to dvdd ?0.3 v to +2 v avdd to pvdd ?0.3 v to +2 v avdd to dvdd ?0.3 v to +2 v digital inputs voltage to dgnd dgnd ? 0.3 v to dvddio + 0.3 v digital outputs voltage to dgnd dgnd ? 0.3 v to dvddio + 0.3 v analog inputs to agnd agnd ? 0.3 v to avdd + 0.3 v maximum junction temperature (t j max ) 125c storage temperature range ?65c to +150c infrared reflow soldering (20 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal performance to reduce power consumption when using the part the user is advised to turn off any unused adcs . the junction temperature must always stay below the maximum junction temperature (t j max ) of 125c. this equation shows how to calculate the junction temperature: t j = t a max + ( ja w max ) where: t a max = 85c. ja = 30c/w. w max = (( av d d i av d d ) + ( dvdd idvdd ) + ( dvddio idvddio ) + ( pvdd ipvdd )) . thermal specifications table 6. thermal characteristics symbol test conditions typ unit junction-to-case thermal resistance jc 4-layer pcb with solid ground plane 7 c/w junction-to-ambient thermal resistance ja 4-layer pcb with solid ground plane (still air) 30 c/w esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adv7403 rev. spa | page 10 of 24 pin configuration and fu nction descriptions 26 p6 27 p5 28 p4 29 p26 30 p25 31 p24 32 p23 33 p22 34 p21 35 dclk_in 36 llc1 37 xtal1 38 xtal 39 dvdd 2 3 4 7 6 5 1 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 11 74 73 72 69 70 71 75 68 67 66 64 63 62 61 60 59 58 57 56 55 54 53 52 51 65 40 dgnd 41 p3 42 p2 43 p1 44 p0 45 p20 46 elpf 47 pvdd 48 pvdd 49 agnd 50 agnd 05431-002 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pin 1 adv7403 lqfp top view (not to scale) p11 p32 p31 int cs/hs dgnd dvddio p15 p14 p13 p12 dgnd dvdd p29 p28 sfl/sync_out sclk2 dgnd dvddio sda2 p10 p9 p8 p27 p7 ain2 ain8 ain1 ain7 sog ain9 ain3 test1 agnd capy1 capy2 avdd refout cml agnd bias capc1 capc2 test0 ain10 ain4 ain11 ain5 ain12 fb f i e l d / d e d e _ i n s o y a i n 6 a l s b s d a 1 s c l k 1 p 4 0 p 3 9 v s _ i n h s _ i n / c s _ i n p 3 8 p 3 7 d g n d d v d d p 1 9 p 1 7 p 1 6 p 3 6 p 3 5 p 3 4 v s p 3 3 p 1 8 r e s e t figure 2. pin configuration table 7. pin function descriptions pin no. mnemonic type function 5, 11, 17, 40, 89 dgnd g digital ground. 49, 50, 60, 66 agnd g analog ground. 6, 18 dvddio p digital i/o supply voltage (3.3 v). 12, 39, 90 dvdd p digital core supply voltage (1.8 v). 63 avdd p analog supply voltage (3.3 v). 47, 48 pvdd p pll supply voltage (1.8 v). 51 fb i fast switch overlay input. this pin switches between cvbs and rgb analog signals. 54, 56, 58, 72, 74, 76, 53, 55, 57, 71, 73, 75 ain1 to ain12 i analog video input channels. 42, 41, 28, 27, 26, 25, 23, 22, 10, 9, 8, 7, 94, 93, 92, 91 p2 to p9, p12 to p19 o video pixel output port. 44, 43, 21, 20, 45, 34, 33, 32, 31, 30, 29, 24, 14, 13 p0 to p1, p10 to p11, p20 to p21, p22 to p25, p26 to p29 i/o video pixel input/output port. 2, 1, 100, 97, 96, 95, 88, 87, 84, 83 p31 to p40 i video pixel input port.
adv7403 rev. spa | page 11 of 24 pin no. mnemonic type function 3 int o interrupt. this pin can be active low or acti ve high. when sdp/cp status bits change, this pin triggers. the set of events that tri ggers an interrupt is under user control. 4 hs/cs o hs is a horizontal synchronization output si gnal (sdp and cp modes). cs is a digital composite synchronization signal (and can be selected while in cp mode). 99 vs o vertical synchronization output signal (sdp and cp modes). 98 field/de o field is a field synchronizat ion output signal (all interl aced video modes). this pin also can be enabled as a data enable signal (de) in cp mode to allow direct connection to a hdmi/dvi tx ic. 81, 19 sda1, sda2 i/o i 2 c port serial data input/outp ut pins. sda1 is the data line for the control port, and sda2 is the data line fo r the vbi readback port. 82, 16 sclk1, sclk2 i i 2 c port serial clock input (max clock rate of 400 khz). sclk1 is the clock line for the control port and sclk2 is the clock li ne for the vbi data readback port. 80 alsb i this pin selects the i 2 c address for the adv7403 control and vbi readback ports. alsb set to logic 0 sets the address for a writ e to control port of 0x40 and the readback address for the vbi port of 0x21. alsb set to a logic high sets the address for a write to control port of 0x42 and the readback address for the vbi port of 0x23. 78 reset i system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the adv7403 circuitry. 36 llc1 o llc1 is a line-locked output clock for the pi xel data (range is 12.825 mhz to 140 mhz for adv7403kstz-140; 12.825 mhz to 110 mhz for adv7403bstz-110. 38 xtal i input pin for 28.63636 mhz crystal, or can be overdriven by an external 3.3 v, 28.63636 mhz clock oscillator so urce to clock the adv7403. 37 xtal1 o this pin should be connected to the 28.63636 mh z crystal or left as a no connect if an external 3.3 v 28.63636 mhz clock oscillator so urce is used to clock the adv7403. in crystal mode the crystal must be a fundamental crystal. 46 elpf o the recommend external loop filter must be connected to this elpf pin. 70 test0 nc this pin should be left un connected or alternaltely tie to agnd. 59 test1 o this pin should be left unconnected. 15 sfl/sync_out o subcarrier frequency lock (sfl). this pin contains a serial output stream, which can be used to lock the subcarrier frequenc y when this decoder is connected to any analog devices digital video encoder. syn c_out is the sliced sync output signal available only in cp mode. 64 refout o internal voltage reference output. 65 cml o common-mode level pin (c ml) for the internal adcs. 61, 62 capy1, capy2 i adc capacitor network. 68, 69 capc1, capc2 i adc capacitor network. 67 bias o external bias setting pin. connect the re commended resistor (1.35 k) between pin and ground. 86 hs_in/cs_in i can be configured in cp mode to be either a digital hs input signal or a digital cs input signal used to extract timing in a 5-wire or 4-wire rgb mode. 85 vs_in i vs input signal. used in cp mode for 5-wire timing mode. 79 de_in i data enable input signal. used in 24-bi t digital input port mode (for example, processing 24-bit rgb data from a dvi rx ic). 35 dclk_in i clock input signal. used in 24-bit digital in put mode (for example, processing 24-bit rgb data from a dvi rx ic) and a lso in digital cvbs input mode. 52 sog i sync on green input. used in embedded sync mode. 77 soy i sync on luma input. used in embedded sync mode.
adv7403 rev. spa | page 12 of 24 timing diagrams sda1/sda2 sclk1/sclk2 t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 05431-003 figure 3. i 2 c timing 05431-004 llc1 p0?p29, vs, hs, field/de, sfl/sync_out t 9 t 10 t 12 t 11 figure 4. pixel port and control sdr output timing (sd core) llc1 p0?p29, vs, hs, field/de t 14 t 9 t 13 t 10 05431-005 figure 5. pixel port and control sdr output timing (cp core) 05431-006 llc1 p6?p9, p10?p19 t 16 t 18 t 15 t 17 figure 6. pixel port and control ddr output timing (cp core) t 9 t 10 t 20 t 19 dclk_in de_in hs_in vs_in control inputs 05431-008 p0?p1, p10?p11, p20?p21, p22?p29, p31?p32, p33?p40 figure 7. digital input port and control input timing
adv7403 rev. spa | page 13 of 24 detailed functionality analog front end ? four 140 mhz (adv7403kstz-140), noise shaped video, 12-bit adcs enable true 10-bit video decoder ? 12 analog input channel mux enables multisource connection without the requirement of an external mux ? four current and voltage clamp control loops ensure any dc offsets are removed from the video signal ? scart functionality and sd rgb overlay on cvbs controlled by fast blank input ? four antialias filters to remove out of band noise on standard definition input video signals. sdp pixel data output modes ? 8-/10-bit itu-r bt.656 4:2:2 ycrcb with embedded time codes and/or hs, vs, and field ? 16-/20-bit ycrcb with embedded time codes and/or hs, vs, and field ? 24-/30-bit ycrcb with embedded time codes and/or hs, vs, and field cp pixel data output modes ? single data rate (sdr) 8-/10-bit 4:2:2 ycrcb for 525i, 625i ? single data rate (sdr) 16-/20-bit 4:2:2 ycrcb for all standards ? single data rate (sdr) 24-/30-bit 4:4:4 ycrcb/rgb for all standards ? double data rate (ddr) 8-/10-bit 4:2:2 ycrcb for all standards ? double data rate (ddr) 12-bit 4:4:4 ycrcb/rgb for all standards composite and s-vi deo processing ? support for ntsc (j, m, 4.43), pal (b, d, i, g, h, m, n, 60) and secam b/d/g/k/l standards in the form of cvbs and s-video ? superadaptive 2d 5-line comb filters for ntsc and pal give superior chrominance and luminance separation for composite video ? full automatic detection and autoswitching of all worldwide standards (pal/ntsc/secam) ? automatic gain control with white peak mode ensures the video is always processed without loss of the video processing range ? adaptive digital line length tracking (adllt?) ? proprietary architecture for locking to weak, noisy, and unstable sources from vcrs and tuners ? if filter block compensates for high frequency luma attenuation due to tuner saw filter ? chroma transient improvement (cti) ? luminance digital noise reduction (dnr) ? color controls include hue, brightness, saturation, contrast, and cr and cb offset controls ? certified macrovision copy protection detection on composite and s-video for all worldwide formats (pal/ntsc/secam) ? 4 oversampling (54 mhz) for cvbs, s-video, and yuv modes ? line-locked clock output (llc) ? letterbox detection supported ? free-run output mode provides stable timing when no video input is present ? vertical blanking interval data processor ? teletex t ? video programming system (vps) ? vertical interval time codes (vitc) ? closed captioning (cc) and extended data service (eds) ? wide screen signaling (wss) ? copy generation management system (cgms) ? gemstar? 1/2 electronic program guide compatible ? clocked from a single 28.63636 mhz crystal ? subcarrier frequency lock (sfl) output for downstream video encoder ? differential gain typically 0.4% ? differential phase typically 0.4
adv7403 rev. spa | page 14 of 24 component video processing ? formats supported include 525i, 625i, 525p, 625p, 720p, 1080i, and many other hdtv formats ? automatic adjustments include gain (contrast) and offset (brightness); manual adjustment controls are also supported ? support for analog component yprpb/rgb video formats with embedded sync or with separate hs, vs, or cs ? any-to-any, 3 3 color space conversion matrix supports ycrcb-to-rgb and rgb-to-ycrcb ? standard identification (stdi) enables system level component format detection ? synchronization source polarity detector (sspd) deter- mines the source and polarity of the synchronization signals that accompany the input video ? certified macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p) ? free-run output mode provides stable timing when no video input is present ? arbitrary pixel sampling support for nonstandard video sources rgb graphics processing ? 140 msps conversion rate supports rgb input resolutions up to 1280 1024 @ 75 hz (sxga ); ( 110 msps conversion rate for adv7403bstz-110) ? automatic or manual clamp and gain controls for graphics modes ? contrast and brightness controls ? 32-phase dll allows optimum pixel clock sampling ? automatic detection of sync source and polarity by sspd block ? standard identification is enabled by stdi block ? rgb can be color space converted to ycrcb and decimated to a 4:2:2 format for video centric backend ic interfacing ? data enable (de) output signal supplied for direct connection to hdmi/dvi tx ic ? arbitrary pixel sampling support for nonstandard video sources digital video input port ? supports raw 8-/10-bit cvbs data from digital tuner ? support for 24-bit rgb input data from dvi rx chip, output converted to ycrcb 4:2:2 ? support for 24-bit 4:4:4, 16-/20-bit 4:2:2 525i, 625i, 525p, 625p, 1080i, 720p, vga to sxga @ 60 hz input data from hdmi rx chip, output converted to 16-bit 4:2:2 ycrcb general features ? hs, vs, and field output signals with programmable position, polarity, and width ? programmable interrupt request output pin, int , signals sdp/cp status changes ? supports two i 2 c host port interfaces (control and vbi) ? low power consumption: 1.8 v digital core, 3.3 v analog and digital i/o, low power power-down mode, and green pc mode ? industrial temperature range (?40c to +85c) (adv7403bstz-110) ? 140 mhz speed grade (adv7403kst-140) ? 100-lead, 14 mm 14 mm, pb-free lqfp
adv7403 rev. spa | page 15 of 24 detailed description analog front end the adv7403 analog front end comprises four noise shaped video, 12-bit adcs that digitize the analog video signal before applying it to the sdp or cp (see table 8 for sampling rates). the analog front end uses differential channels to each adc to ensure high performance in a mixed-signal application. the front end also includes a 12-channel input mux that enables multiple video signals to be applied to the adv7403. current and voltage clamps are positioned in front of each adc to ensure that the video signal remains within the range of the converter. fine clamping of the video signals is performed downstream by digital fine clamping either in the cp or sdp. optional antialiasing filters are positioned in front of each adc. these filters can be used to band-limit standard definition video signals, removing spurious, out-of-band noise. the adcs are configured to run in 4 oversampling mode when decoding composite and s-video inputs; 2 oversampling is performed for component 525i, 625i, 525p, and 625p sources. all other video standards are 1 oversampled. oversampling the video signals reduces the cost and complexity of external anti-aliasing filters with the benefit of an increased signal-to- noise ratio (snr). the adv7403 can support simultaneous processing of cvbs and rgb standard definition signals to enable scart compat- ibility and overlay functionality. a combination of cvbs and rgb inputs can be mixed and output under control of i 2 c registers and the fast blank pin. table 8: maximum adc sampling rates model maximum adc sampling rate adv7403bstz-110 110 mhz adv7403kstz-140 140mhz standard definition processor the sdp section is capable of decoding a large selection of baseband video signals in composite s-video and yuv formats. the video standards supported by the sdp include pal b/d/i/g/h, pal60, pal m, pal n, ntsc m/j, ntsc 4.43, and secam b/d/g/k/l. the adv7403 can automatically detect the video standard and process it accordingly. the sdp has a 5-line super adaptive 2-d comb filter that gives superior chrominance and luminance separation when decod- ing a composite video signal. this highly adaptive filter auto- matically adjusts its processing mode according to video standard and signal quality with no user intervention required. the sdp has an if filter block that compensates for attenuation in the high frequency luma spectrum due to tuner saw filter. the sdp has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue. the adv7403 implements a patented adaptive-digital-line- length-tracking (adllt) algorith m to track varying video line lengths from sources such as a vcr. adllt enables the adv7403 to track and decode poor quality video sources such as vcrs, noisy sources from tuner outputs, vcd players, and camcorders. the sdp also contains a chroma transient improvement (cti) processor. this processor increases the edge rate on chroma transitions, resulting in a sharper video image. the sdp can process a variety of vbi data services, such as teletext, closed captioning (cc), wide screen signaling (wss), video programming system (vps), vertical interval time codes (vitc), copy generation management system (cgms), gemstar 1/2, and extended data service (xds). the adv7403 sdp section has a macrovision 7.1 detection circuit that allows it to detect types i, ii, and iii protection levels. the decoder is also fully robust to all macrovision signal inputs. component processor the cp section is capable of decoding/digitizing a wide range of component video formats in any color space. component video standards supported by the cp are 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, vga up to sxga @ 75 hz, (adv7403kstz-140 only) and many other standards not listed here. the cp section of the adv7403 contains an agc block. when no embedded sync is present, the video gain can be set manually. the agc section is followed by a digital clamp circuit that ensures the video signal is clamped to the correct blanking level. automatic adjustments within the cp include gain (contrast) and offset (brightness); manual adjustment controls are also supported. a fully programmable any-to-any, 3 3 color space conversion matrix is placed between the analog front end and the cp section. this enables yprpb-to-rgb and rgb-to-ycrcb conversions. many other standards of color space can be implemented using the color space converter. the output section of the cp is highly flexible. it can be config- ured in single data rate mode (sdr) with one data packet per clock cycle or in a double data rate (ddr) mode where data is presented on the rising and falling edges of the clock. in sdr mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. in these modes, hs, vs, and field/de (where applicable) timing reference signals are provided. in ddr mode, the adv7403 can be configured in an 8-/10-bit 4:2:2 ycrcb or 12-bit 4:4:4 rgb/ ycrcb pixel output interface with corresponding timing signals.
adv7403 rev. spa | page 16 of 24 the adv7403 is capable of supporting an external dvi/ hdmi receiver. the digital interface expects 24-bit 4:4:4 or 16-/20-bit 4:2:2 bit data (either graphics rgb or component video ycrcb), accompanied by hs, vs, de, and a fully synchronous clock signal. the data is processed in the cp and output as 16-bit 4:2:2 ycrcb data. the cp section contains circuitry to enable the detection of macrovision encoded yprpb signals for 525i, 625i, 525p, and 625p. it is designed to be fully robust when decoding these types of signals. vbi extraction of cgms data is performed by the cp section of the adv7403 for interlaced, progressive, and high definition scanning rates. the data extracted can be read back over the i 2 c interface. for more detailed product information about the adv7403, contact your local adi sales office or email video.products@analog.com.
adv7403 rev. spa | page 17 of 24 pixel input/output formatting table 9. sdp, cp pixel input/output pin map (p19 to p0) processor, format, pixel port pins p[19:0] and mode 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdp video out, 8-bit, 4:2:2 ycrcb[7:0] out - - - - - - - - - - - - sdp video out, 10-bit, 4:2:2 ycrcb[9:0] out - - - - - - - - - - sdp video out, 16-bit, 4:2:2 y[7:0] out - - crcb[7:0] out - - sdp video out, 20-bit, 4:2:2 y[9:0] out crcb[9:0] out sdp video out, 24-bit, 4:4:4 y[7:0] out - - cb[7:0] out - - sdp video out, 30-bit, 4:4:4 y[9:0] out cb[9:0] out sm-sdp digital tuner input[1] output choices are the same as video out 16-/20-bit or pseudo 8-/10-bit ddr cp 8-bit, 4:2:2, ddr d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - - - - - - - cp 10-bit, 4:2:2, ddr d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - - - - - cp 12-bit, 4:4:4, rgb ddr d7 d6 d5 d4 d3 d2 d1 d0 - - d11 d10 d9 d8 - - - - - - cp video out, 16-bit, 4:2:2 cha[7:0] out (for example, y[7:0]) - - chb/c[7:0] out (for example, cr/cb[7:0]) - - cp video out, 20-bit, 4:2:2 cha[9:0] out (for example, y[9:0]) chb/c[9:0] out (for example, cr/cb[9:0]) cp video out, 24-bit, 4:4:4 cha[7:0] out (for example, g[7:0]) - - chb[7:0] out (for example, b[7:0]) - - cp video out, 30-bit, 4:4:4 cha[9:0] out (for example, g[9:0]) chb[9:0] out (for example, b[9:0]) sm-cp hdmi receiver support, 24-bit, 4:4:4 input cha[7:0] out (for example, y[7:0]) r[5:4] in chb/c[7:0] out (for example, cr/cb[7:0]) r[1:0] in sm-cp hdmi receiver support 16-bit pass-through cha[7:0] out (for example, y[7:0]) - - chb/c[7:0] out (for example, cr/cb[7:0]) - - sm-cp hdmi receiver support, 20-bit, pass-through cha[9:0] out (for example, y[9:0]) chb/c[9:0] out (for example, cr/cb[9:0])
adv7403 rev. spa | page 18 of 24 table 10. sdp, cp pixel input/ output pin map (p40 to p20) processor, format, pixel port pins p[40:31], p[29:20] and mode 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 20 sdp video out, 8-bit, 4:2:2 - - - - - - - - - - - - - - - - - - - - sdp video out, 10-bit, 4:2:2 - - - - - - - - - - - - - - - - - - - - sdp video out, 16-bit, 4:2:2 - - - - - - - - - - - - - - - - - - - - sdp video out, 20-bit, 4:2:2 - - - - - - - - - - - - - - - - - - - - sdp video out, 24-bit, 4:4:4 - - - - - - - - - - cr[7:0] out - - sdp video out, 30-bit, 4:4:4 - - - - - - - - - - cr[9:0] out sm-sdp digital tuner input[1] dcvbs[9:0] in - - - - - - - - - - cp 8-bit, 4:2:2, ddr - - - - - - - - - - - - - - - - - - - - cp 10-bit, 4:2:2, ddr - - - - - - - - - - - - - - - - - - - - cp 12-bit, 4:4:4, rgb ddr - - - - - - - - - - - - - - - - - - - - cp video out, 16-bit, 4:2:2 - - - - - - - - - - - - - - - - - - - - cp video out, 20-bit, 4:2:2 - - - - - - - - - - - - - - - - - - - - cp video out, 24-bit, 4:4:4 input - - - - - - - - - - chc[7:0] out (for example, r[7:0]) - - cp video out, 30-bit, 4:4:4 input - - - - - - - - - - chc[9:0] out (for example, r[9:0]) sm-cp hdmi receiver support, 24-bit, 4:4:4 input g[7:0] in r[7:6] in b[7:0] in r[3:2] in sm-cp hdmi receiver support, 16-bit, pass-through cha[7:0] in (for example, y[7:0]) - - chb/c[7:0] in (for example, cr/cb[7:0]) - - sm-cp hdmi receiver support, 20-bit, pass-through cha[9:0] in (for example, y[9:0]) chb/c[9:0] in (for example, cr/cb[9:0])
adv7403 rev. spa | page 19 of 24 recommended external loop filter components the external loop filter components for the elpf pin should be placed as close as possible to the respective pins. figure 8 shows the recommended component values. 05431-007 1.69k 82nf 10nf pvdd = 1.8v pin 46?elpf figure 8. elpf components
adv7403 rev. spa | page 20 of 24 typical connection diagram 75 75 75 75 75 75 75 75 56 agnd 10nf 0.1 f 10nf 0.1 f 10nf 0.1 f dvdd_1.8v dgnd u1 bypass capacitors 10nf 0.1 f 10nf 0.1 f dvddio dgnd u1 bypass capacitors 10nf 0.1 f agnd pvdd_1.8v 10nf 0.1 f agnd avdd_3.3v 75 green blue red rgb graphics p5?2 p5?3 p5?1 p5?13 p5?14 p6?5 p6?6 p5?7 p5?8 p5?10 hs_in vs_in 1 3 5 21 2 4 6 p4 scart_21_pin 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 43 21 p8 mini-din-4 s-video sog ain1 ain2 ain3 ain4 ain5 ain6 soy ain10 ain11 ain12 ain7 ain8 ain9 capc2 capc1 capy2 capy1 cml refout bias xtal xtal1 elpf sda sclk sda2 sclk2 alsb reset 1 3 2 4 19 19 20 cvbs/y cvbs p9 agnd 19 56 0.1 f pvdd pvdd avdd dvdd dvdd dvdd dvddio dvddio de_in p40 p39 p38 p37 p36 p35 p34 p33 p32 p31 int dclk_in p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 llc1 hs vs field href/hs_in vref/vs_in sfl/sync_out fb test1 test0 avss avss pvss pvss dvssio dvssio dvss dvss dvss adv7403 33 vp41 79 33 vp40 83 33 vp39 84 33 vp38 87 33 vp37 88 33 vp36 95 33 vp35 96 33 vp34 97 33 vp33 100 33 vp32 1 33 vp31 2 33 vp30 3 33 vp29 13 33 vp28 14 33 vp27 24 33 vp26 29 33 vp25 30 33 vp24 31 33 vp23 32 33 vp22 33 33 vp21 34 33 vp20 45 33 vp19 91 33 vp18 92 33 vp17 93 33 vp16 94 33 vp15 7 33 vp14 8 33 vp13 9 33 vp12 10 33 vp11 20 33 vp10 21 33 vp09 22 33 vp08 23 33 vp07 25 33 vp06 26 33 vp05 27 33 vp04 28 vp[00:41] int dclck_in 33 vp03 41 33 vp02 42 33 vp01 43 33 vp00 44 100 4 100 99 100 98 100 86 100 85 33 15 hs vs field hs_in vs_in sfl/sync_ou t 100 36 10nf 0.1 f 10 f 0.1 f agnd 10nf 0.1 f 10 f 0.1 f agnd 0.1 f 10 f 10 f 0.1 f 2.7k 2.7k y2 28.63636mhz 1m 47pf 1 47pf 1 dgnd 10nf 82nf pvdd_1.8v 1.69k 100 100 5.6k sda sclk reset dvddio k1 k2 bat54c dvddio pvdd_1.8v dvdd_1.8v avdd_3.3v dvddio u1 47 48 63 12 39 90 6 18 c22 1nf c94 1nf d1 bzx399-c3v3 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f y c agnd 1 load cap values are dependant on crystal attributes agnd pr/pb pb/pr y red/c green f_blnk blue phono3 agnd 05431-009 u1 bypass capacitors 10k 35 70 66 60 49 50 5 17 11 40 89 llc1 52 54 56 58 72 74 76 77 71 73 75 53 55 57 69 68 62 61 65 64 67 38 37 46 81 82 19 16 80 78 51 59 agnd + + p7 16 2 11 15 agnd dgnd figure 9. adv7403 typical connection diagram
adv7403 rev. spa | page 21 of 24 outline dimensions compliant to jedec standards ms-026-bed top view (pins down) 1 25 26 51 50 75 76 100 0.50 bsc lead pitch 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 14.20 14.00 sq 13.80 16.20 16.00 sq 15.80 051706-a figure 10. 100-lead low profile quad flat package [lqfp] (st-100) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adv7403bstz-110 2 ?40c to +85c 100-lead low profile quad flat package (lqfp) st-100 adv7403kstz-140 2 0c to 70c 100-lead low profile qu ad flat package (lqfp) st-100 eval-adv7403ebm evaluation board 1 the adv7403 is a pb-free, environmentally friendly product. it is man ufactured using the most up -to-date materials and process es. the coating on the leads of each device is 100% pure sn electrop late. the device is suitable fo r pb-free applications, and is ab le to withstand surface-mount so ldering at up to 255c (5c). in addition, it is backward-compatible with conventional snpb soldering processes. this means that the electroplated sn coating can be solde red with snpb solder pastes at conventional reflow temperatures of 220c to 235c. 2 z = pb-free part.
adv7403 rev. spa | page 22 of 24 notes
adv7403 rev. spa | page 23 of 24 notes
adv7403 rev. spa | page 24 of 24 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05431C0C9/05(spa)

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